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ASM++: a modern Algorithmic State Machine methodology for RTL designs

Compiler directives

Code boxes can be used to write HDL expressions, but also to introduce several directives that will be effective only at compilation time:

Directive	Comments
#define <name> <string>	It defines a substitution chain, just as in C/C++, but its scope is different: they are seen only on their module/entity. For a global scope use #global instead.
#echo <string>[;]	Generates a compiler message to the user. Example: #echo "Hello world from ASM++ Compiler!"
#error <string>[;]	Generates a compiler error message to the user, especially useful when used with conditional compilation. Example: #error "Parameter out of range!"
#global <name> <string>	It is the same than a #define, but its value is seen at all designs. This directive can be used only at the external section of any design.
#language {VHDL, Verilog}[;]	It indicates the style of HDL expressions used in code boxes and any other ASM box. This directive is optional because in most situations the ASM++ compiler detects the input language automatically.
#locate <port_name> at <string>[;]	Specifies a physical location for a port signal. Nowadays, only individual ports may be assigned.

Compiler variables

Designers may use "signals" or "wires" to describe the behavior of the circuit and, thus, to build digital logic. In addition, they may use compiler variables, valid only at compilation time, to help on the description of those signals, usually on complex designs. Nowadays there are variables of two kinds, and they are identified by a dollar ('$') sign:

Kind	Example	Description
String	$one = "Hello"; $two := $one + " World!";	Stores a text string on a variable. Verilog designers must use the '=' operand, but VHDL designers must use ':=' instead.
Integer	$five := 5; $sixty = 30 + 6 * $five;	Stores an integer number on a variable. Verilog designers must use the '=' operand, but VHDL designers must use ':=' instead.

The main difference between 'signals' and 'variables' is that 'signals' describe operations of the digital circuit, executed by the circuit when running, while 'variables' describe compiler operations, executed at compilation time.

Compiler command line mode

ASM++ Compiler can be executed using the graphical possibilities of Windows XP, but it also can be executed through command line orders, thus a 'makefile' may use this compiler to generate HDL code. The syntax for this command is shown following:

drive:\path>  asmCompiler  [-verbose] [-no_verbose] [-build_all] [-no_build_all]  <file_name.vdx>

The meaning of its options is shown following:

Element	Type	Comments
-verbose	By default	Specifies that ASM++ Compiler must generate log information through a file named file_name.log.
-no_verbose	Optional	Specifies that ASM++ Compiler must not generate any log information.
-build_all	Optional	Specifies that ASM++ Compiler must regenerate all intermadiate and final files.
-no_build_all	By default	Specifies that ASM++ Compiler must avoid compilation of previously processed untouched files.
file_name.vdx	Required	Specifies the path and name of one VDX file to process it (and all children files it includes).