ASM++: a modern Algorithmic State Machine methodology for RTL designs
Rules of ASM++ language
ASM++ diagrams must fulfill the following rules:
Any ASM++ diagram must have at least one state box and any number of synchronous, asynchronous and decision boxes between state boxes.
When an output code is desired, more boxes are required: at least a header box to describe the module/entity name, another box
to implement the I/O interface, eventually one or more code boxes are needed to specify the name and size of its internal signals;
at least one synchronization box is needed on sequential circuits and one initialization box must be instantiated for each thread
with two or more states, to specify the reset signal and the first state after a reset pulse.
All written operations between two state boxes will be executed in parallel. If any signal receives different values in the same state,
only the last assignment of each path will be effective.
After a decision box, both branches may join in the same state in a forward fashion, but never backwards.
Any back path must join the state at the state box, or at any other state box.
Outputs and internal signals may exhibit a synchronous behavior (called "assignments" and defined through rectangular boxes)
or an asynchronous behavior (named "assertions", when using boxes of bent sides), but never both. An error is considered
when a signal is synchronously assigned with rectangular boxes and asynchronously asserted using boxes with bent sides.
When using VHDL, internal signals must be declared as "signal"; Verilog users may declare them as "reg" or "wire" ("wor" and "wand"
have not been implemented yet),
depending on their synchronous or asynchronous behavior; for both languages, all assignments and assertions will be described
using the '<=' operator.
When using a "default box", all included signals will get their assigned values on those situations where nothing is specified;
otherwise, synchronous signals will keep their last value, while asynchronous signals will behave in such a way that minimize
the generated combinational logic.
Only one execution thread may assign or assert values to each signal.
Only synchronous signals and outputs can be initialized through a reset box.
The synchronization boxes affect all the later boxes: it is possible to find several synchronization boxes
in those circuits with several threads, but never on the same branch. A circuit can lack these boxes if
its behavior is completely asynchronous.
Once separated through a double line, two different threads cannot join anyway.
