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ASM++: a modern Algorithmic State Machine methodology for RTL designs

Compiler syntax

ASM++ charts are divided in three sections, as seen at the figure below, that describes the syntax of these diagrams:

• The "algorithmic" section describes the behavior of the circuit through a net of states that may execute several operations in a cycle driven parallel fashion.
• A "declarative" section, starting at each header box and ending at the first state box of each thread, may be used to declare internal signals, external ports, clock signals, reset sequences, default values, and so on.
• Finally, an "external" section, before any header box, allow designers to specify global definitions or include other files for hierarchical design.

On these charts, all operations and conditions are expressed using either VHDL or Verilog hardware description languages. This HDL symbiosys improve designer's productivity, because HDL expressions are easy to learn and ASM++ charts allow designers to decide when and where they want to locate their operations.

When using VHDL designers must follow the syntax expressed through the following trumpet diagram [2]:

When using Verilog, the following trumpet diagram must be used instead [3]: