epYme documentation |
ASM++: a modern Algorithmic State Machine methodology for RTL designs
ASM++ Compiler
ASM++ Compiler has been developed by epYme workgroup
at the University of Valladolid (Spain) in collaboration
with eZono AG (Jena, Germany)
and ISEND S.A. (Boecillo, Valladolid, Spain).
This application automatically compiles ASM++ charts and generates VHDL or Verilog code valid for simulation and synthesis.
It reads VDX files from MS Visio 2003/2007 and ConceptDraw.
When processing a chart, ASM++ Compiler reads one or more VDX files and generates VDO (list of objects detected at VDX) and A++ (chart like text description) files. These intermediate files may be used to detect and locate errors. Afterwards, VHDL and/or Verilog files are generated: they are valid for simulation using ModelSim® and synthesis using Xilinx® ISE/Webpack or Altera® Quartus II.
Index · Previous: Examples · Next: Compiler syntax
|
|